MemTest86 10.5 (Build 1000)

Version 10.5 (Build 1000) 19/June/2023​

• New Features
  • Added support for displaying and reporting configured RAM settings for supported chipsets. This includes clock speed, timings, channel mode and voltages.
  • Added support for multiple configurations in a single configuration file. If more than 1 configurations are found, the user is prompted to select a configuration
  • Added support for displaying and reporting DDR5 XMP 3.0 SPD profiles
• Fixes/Enhancements
  • Display configured RAM settings in test screen. Previously, static memory parameters from SPD/SMBIOS were displayed which were not necessarily the actual configured parameters.
  • Include list of all supported SPD profiles (eg. JEDEC, XMP) in reports
  • Changed units from MHz to MT/s when referring to DRAM transfer rate (typically double the clock speed for DDR RAM)
  • Reduced the execution time of hammer test by increase minimum segment size per thread from 128MB to 512MB
  • Reduced the execution time of hammer test by reducing the maximum number of memory segments to hammer from 64 to 32
  • Fixed crash when running the Block Test RAM benchmark
  • Added ECC support for Intel Raptor Lake chipsets
  • Added DIMM temperature support for Intel Broxton chipsets
  • Extended DIMM decoding support for additional Alder Lake and Raptor Lake chipset variants
  • Fixed disabling of hyperthreads for CPUs with hybrid cores
  • Fixed display of negative CPU temperatures
  • Fixed display of negative RAM temperatures
  • Fixed inconsistent slot name in DIMM results screen
  • Fixed text being truncated in DIMM results screen
  • Fixed DIMM error count reporting for 2-slot motherboards
  • Fixed TCP connection to management console being refused for certain Apache configurations
  • Fixed sending corrupted TCP status XML data to management console
  • Fixed error in saving report files due to invalid characters in the file name
  • Updated blacklist

• New Features
  • Added preliminary support for Ryzen Zen 4 DDR5 chip decoding
  • Revised criteria for determining the final result of a memory test
    • PASS – All configured tests were completed without any errors detected
    • FAIL – All configured tests were completed with at least one error was detected or MAXERRCOUNT is exceeded at any point of the test
    • INCOMPLETE PASS – At least one of the configured tests was not completed but no errors were detected
    • INCOMPLETE FAIL –At least one of the configured tests was not completed and at least one error was detected
  • Revised criteria for determining the test result of individual modules
    • PASS – All configured tests were completed and no errors were detected on the module without any undecoded errors
    • FAIL – All configured tests were completed with at least one error detected on the module
    • INCOMPLETE PASS – At least one of the configured tests was not completed but no errors were detected on the module without any undecoded errors
    • INCOMPLETE FAIL –At least one of the configured tests was not completed and at least one error was detected on the module
    • UNKNOWN – No errors were detected on the module but there was at least one undecoded error
• Fixes/Enhancements
  • Added preliminary implementation of ECC injection for Ryzen Zen 4 chipsets
  • Fixed module decoding for DDR4 x16 modules
  • Display ECC error count in message after completing a test pass
  • Fixed incorrect calculation of DDR5 SPD memory bandwidth
  • Added additional columns to module result table in HTML report
  • Removed "Go back to menu" option from the test menu
  • Included '# Tests Completed' in HTML report

Version 10.3 (Build 1000) 24/March/2023​

• New Features
  • Added preliminary support for Ryzen Zen 4 DDR5 module decoding
  • Added support for TCP/IP connection to management console
  • Added 'INCOMPLETE' result in cases where not all tests complete but no errors are detected
  • Added temperatures for all detected DIMMs in HTML/XML report
  • Added ECC support for IBECC polling for Tiger Lake Chipsets
  • Added additional options for 'SKIPDECODE' config parameter to skip based on DDR type
• Fixes/Enhancements
  • Added ECC support for Ryzen zen 4 (60h-6fh)
  • Fixed Intel Raptor Lake model numbers
  • Fixed ECC support for Intel Tiger Lake H and UP3
  • Fixed decode UI layout for DDR4 SO-DIMM 1Rx8
  • Added ECC channel/slot remap workaround for H12SSL-NT
  • Added serial number of failing DIMMs in HTML/XML reports
  • Added DIMM S/N in per DIMM error table in HTML report
  • Include error count for all DIMMs on test failure in HTML/XML report
  • Fixed rank/chip width detection on Intel Tiger Lake chipsets
  • Fixed Chip select hash decoding on Ryzen Zen 2/Zen 4 chipsets
  • Changed 'EXACTSPDS' configuration parameter to accept an array of values
  • Increased main thread wait time if memory error was detected to prevent timeouts
  • Added workaround for UEFI firmware being unable to return correct rendered text dimensions
  • Fixed freeze on some UEFI firmware when attempting to enable main thread during Multi-Processor init
  • Fixed potential boot issues on some MSI Ryzen motherboards
  • Fixed bug in parsing DDR5 SDRAM Density Per Die resulting in incorrect module size
  • Fix premature main thread timeout in parallel mode due to reporting memory errors
  • Fix slot mapping of memory errors for Ryzen AM4 boards
  • Fix bug in determining unknown slot errors when there are consecutive errors for the same address
  • Fix '# Logical Processors' not appearing properly in XML file
  • reduce verbosity of SPD/TSOD SMBus logs

Version 10.2 (Build 1000) 23/Dec/2022​

• New Features
  • Added DIMM and IC decoding for Intel 13th generation Raptor Lake processors
  • Added ECC support for Intel Skylake E on HPE platforms
  • Added support for retrieving DDR5 SPD on Intel Raptor Lake S
  • Added support for retrieving DDR5 SPD on AMD Ryzen 7000 CPUs
  • Added 'SKIPDECODE' configuration parameter to skip the decode results screen after completion of tests (Pro/Site Editions)
• Fixes/Enhancements
  • Modify CHIPMAP config param to include form factor attribute ( e.g. SODIMM, DIMM, etc.)
  • Fix bug applying valid CHIPMAP configurations (when # of CHIPMAP entries is < 7)
  • Include DIMM rank/chip width in HTML report
  • Include DIMM/chip errors in XML file to PXE server
  • Fix UI display of SODIMM chip errors
  • Fix UI display of DIMM x16 chip errors
  • Fix lockup on Mac devices caused by buffer overrun and type overflow in parsing of localization strings
  • Fix handling of measuring text width for empty strings causing lockup on Sandy Bridge CPUs
  • Fix of SPD channel/slot assignment for Intel E5 v3 chipset
  • Fix DIMM result screen to handle boards with unused MC slots ( e.g. Q670EI IM A)
  • Fix SODIMM chip ordering in the result screen
  • Include unknown DIMM/chip errors in HTML/PXE reports

Version 10.1 (Build 1000) 16/Dec/2022​

• New Features
  • Modified CHIPMAP config file parameter to support multiple DIMM configurations (eg. DDR4|DDR5, x8|x16, 1R|2R, 8GB|16GB)
  • Added DIMM and IC decoding for Intel 8th, 9th, 10th and 11th generation processors (Pro/Site editions).
  • Added initial support for Raptor Lake, Tremont and Sapphire Rapids chipsets. This includes accurate retrieval and display of processor speed, core status, temperature information and of core group multipliers
• Fixes/Enhancements
  • Reduced overall image size to allow use of USB flash drives under 1GB
  • Fixed ECC channel/slot error details not displaying correctly
  • Added “Un-decoded” errors to results screen
  • Updated CPU cache speed values to 64bit to prevent overflow errors on faster systems
  • Fixed mapping of SMBIOS slot to SPD when there are duplicate serial numbers
  • Fixed hyperthread detection when max number of CPU threads are limited (eg. 16 in Free edition)
  • Fixed issue allowing multiprocessor cores to exceed max system cores
  • Fixed issues when number of CPU cores exceed MemTest86 version's max core limit
  • Fixed rounding error with DDR5 clock speed
  • Fixed test selection in console only mode

• New Features
  • Added new experimental memory test as Test 14 [DMA test]. This test exercises the disk controller's DMA hardware to perform memory access, bypassing the CPU. The motivation for this test came from discovering a defective RAM module that did not produce errors when accessed via the CPU, but failed when files were read from disk via DMA. As this test is experimental, it shall be disabled by default.
  • DIMM (Pro edition)/chip-level (Site Edition) error detection on limited number of hardware platforms. This includes mid-test error reporting, graphical UI summary report on test completion and per-DIMM/chip error count table in the HTML report.
    • Added new config file parameter, 'CPUMAP', to specify the DRAM chip labeling map. By default, DRAM chips are labeled consecutively starting from U0 (eg. U0, U1,…, U15)
• Fixes/Enhancements
  • Log file name now includes the timestamp
  • Added new blacklist flag 'DISABLE_CPUINFO' for disabling CPU info collection
  • Fixed 'MAXCPUS' config file parameter not being applied
  • Fixed hammer test incorrectly running in single-sided mode in Free version
  • Fixed clock speed measurement failure for ARM chipsets due to cycle count register not being enabled
  • Fixed detection of MAC address used as unique ID for PXE boot
  • Added support for reporting IBECC errors
  • Fixed bug in reading ECC error count registers for various Intel/AMD Ryzen chipsets
  • Fixed reading ECC error status register for Intel Tiger Lake-H and Alder Lake chipsets
  • Fixed ECC detection on Intel Ice Lake-SP chipsets
  • Added ECC detection support for multi-socket Intel Ice Lake-SP chipsets
  • Fixed ECC support for Intel Rocket Lake chipset variant
  • Added ECC support for AMD Ryzen Zen 3 50h-5fh chipset
  • Fixed ECC support for AMD Ryzen Zen 2 chipsets with 2 memory channels
  • Fixed ECC error false positives on Intel Atom C2000 chipsets
  • Added support for retrieving Intel Ice Lake-SP CPU info
  • Added support for retrieving Intel Ice Lake-SP RAM SPD data
  • Added support for retrieving Intel Ice Lake-SP RAM temperature data
  • Added SMBus (SPD) support for Intel Alder Lake-P
  • Enable SMBus on Intel 801-based chipsets if disabled
  • Fixed detection of SPD modules on systems with > 8 SMBus controllers (eg. quad socket systems)
  • Fixed bug in mapping SPD module index to SMBIOS slot index
  • Fixed detection of SPD slot for systems with soldered and removable DIMMs
  • Fixed incorrect calculation of DDR5 transfer bandwidth
  • Fixed DDR5 memory type in SMBIOS not being correctly parsed
  • Fixed identification of data partition in USB flash drive
  • Create 'Benchmark' directory to store RAM benchmark results if it does not already exist
  • Updated blacklist

New Features

• Added new experimental memory test as Test 14 [DMA test]. This test exercises the disk controller's DMA hardware to perform memory access, bypassing the CPU. The motivation for this test came from discovering a defective RAM module that did not produce errors when accessed via the CPU, but failed when files were read from disk via DMA.

Fixes/Enhancements

• Fixed hammer test incorrectly running in single-sided mode in Free version
• Fixed clock speed measurement failure for ARM chipsets due to cycle count register not being enabled
• Fixed bug in reading ECC error count registers for various Intel/AMD Ryzen chipsets
• Fixed reading ECC error status register for Intel Tiger Lake-H and Alder Lake chipsets
• Fixed ECC detection on Intel Ice Lake-SP chipsets
• Fixed ECC support for Intel Rocket Lake chipset variant
• Added ECC support for Ryzen Zen 3 50h-5fh chipset
• Added support for retrieving Intel Ice Lake-SP CPU info
• Added support for retrieving Ice Lake-SP RAM SPD data
• Added support for retrieving Ice Lake-SP RAM temperature data
• Updated blacklist

How to report problems

Either make a post here in the forum, or send us an email at the address listed on our contact page. When reporting an error please provide as much details as possible. If you are running on a USB drive, there should be a log file that has been generated in the EFI/BOOT directory called MemTest86.log. Sending us this will be of great help. Additionally a photograph of the problem would also be useful if possible/applicable.

Version 9.4 (Build 1000) 24/Jan/2022​

• Fixes/Enhancements
  • Added new config file parameter, 'MAXCPUS', for setting the maximum number of CPU logical cores used for testing. By default, this value is 256 (Pro Edition) and 16 (Free Version). This parameter can be set to a maximum value of 512.
  • Added new config file parameter, 'AUTOPROMPTFAIL', for specifying whether to display the test result and ask for user intervention on test failure, even when AUTOMODE is enabled
  • Added new config file naming convention allowing for separate config files depending on memory size: <Memory-size-in-GB>GB-mt86.cfg
  • Fixed memory size calculation to use rounding instead of truncation
  • Display PASS message box in yellow (instead of green) on test completion if corrected ECC errors were detected
  • Display error message if no valid SPD.spd file was found when SPDMATCH=1
  • Display error message if no SPD modules were detected when SPDMATCH=1
  • Display error message and exit MemTest86 when failing to measure CPU clock speed during startup
  • Updated XML message to include CPU info & SMBIOS info sent to PXE server/management console
  • Added ECC Support for Intel Tiger Lake H chipset
  • Added ECC Support for Intel Rocket Lake chipset
  • Added ECC Support for Intel Alder Lake chipset
  • Added ECC Support for Intel Ice Lake-SP chipset
  • Added support for retrieving CPU info for Intel Elkhart Lake chipset
  • Added support for retrieving DIMM temperatures (TSOD) for Intel Alder Lake chipset
  • Fixed issue with measuring ARM64 CPU clock speed due to CPU cycle counter (PMCCNTR) being disabled
  • Fixed HTML report to display error bit map in text when copying/pasting
  • Fixed Linux badram entries in HTML report to be page size aligned (4096 bytes)
  • Fixed parsing bug with SPD.spd file when whitespace appears at the end of each line
  • Fixed issues with displaying RAM SPD DDR5-specific info
  • Fixed support for limited number of command line parameters in Free version
  • Fixed bug in overflowing text in SPD info screen
  • Fixed REPORTNUMWARN config file parameter not being written when saving config file
  • Included Serva PXE server configuration file in Site Edition package
  • Updated blacklist with Dell Precision 7760 screen display issues

Version 9.4 (Build 1000) 24/Jan/2022​

• Fixes/Enhancements
  • Added new config file parameter, 'MAXCPUS', for setting the maximum number of CPU logical cores used for testing. By default, this value is 256 (Pro Edition) and 16 (Free Version). This parameter can be set to a maximum value of 512.
  • Added new config file parameter, 'AUTOPROMPTFAIL', for specifying whether to display the test result and ask for user intervention on test failure, even when AUTOMODE is enabled
  • Added new config file naming convention allowing for separate config files depending on memory size: <Memory-size-in-GB>GB-mt86.cfg
  • Fixed memory size calculation to use rounding instead of truncation
  • Display PASS message box in yellow (instead of green) on test completion if corrected ECC errors were detected
  • Display error message if no valid SPD.spd file was found when SPDMATCH=1
  • Display error message if no SPD modules were detected when SPDMATCH=1
  • Display error message and exit MemTest86 when failing to measure CPU clock speed during startup
  • Updated XML message to include CPU info & SMBIOS info sent to PXE server/management console
  • Added ECC Support for Intel Tiger Lake H chipset
  • Added ECC Support for Intel Rocket Lake chipset
  • Added ECC Support for Intel Alder Lake chipset
  • Added ECC Support for Intel Ice Lake-SP chipset
  • Added support for retrieving CPU info for Intel Elkhart Lake chipset
  • Added support for retrieving DIMM temperatures (TSOD) for Intel Alder Lake chipset
  • Fixed issue with measuring ARM64 CPU clock speed due to CPU cycle counter (PMCCNTR) being disabled
  • Fixed HTML report to display error bit map in text when copying/pasting
  • Fixed Linux badram entries in HTML report to be page size aligned (4096 bytes)
  • Fixed parsing bug with SPD.spd file when whitespace appears at the end of each line
  • Fixed issues with displaying RAM SPD DDR5-specific info
  • Fixed support for limited number of command line parameters in Free version
  • Fixed bug in overflowing text in SPD info screen
  • Fixed REPORTNUMWARN config file parameter not being written when saving config file
  • Included Serva PXE server configuration file in Site Edition package
  • Updated blacklist with Dell Precision 7760 screen display issues

Version 9.3 (Build 1000) 6/Oct/2021​

• Fixes/Enhancements
  • Support custom test definitions specified by a configuration file. A custom test definition consists of an existing test algorithm, specific test pattern, cache settings, and number of iterations. Custom test definitions are enabled by specifying the TESTCFGFILE parameter (Pro Edition only)
  • Fixed incorrectly formatted XML Status/TestResult files sent to PXE/TFTP server (Site Edition only)
  • Fixed incorrect reporting of error endianess for 128-bit test
  • Fixed bug in displaying/logging ECC error channel/slot number
  • Fixed report/log files not being saved correctly for non-standard USB flash drive installs
  • Improved responsiveness of pattern string updated on screen
  • Display row hammer warning, if applicable, in test completion popup message
  • Fixed ECC error reporting on AMD Ryzen chipsets to include channel/slot information
  • Fixed ECC error reporting on AMD Ryzen chipsets with 8 memory channels
  • Improved robustness of ECC error reporting for Intel Atom C2000 chipsets
  • Fixed retrieval of DDR4 SPD bytes on Intel Alder Lake chipsets
  • Added support for parsing DDR3 Module Manufacturer’s Specific Data
  • Updated blacklist with additional Surface Pro models with display issues