Synopsys and TSMC Accelerate 2.5D/3DIC Designs with CoWoS-S and Integrated Fan-Out Certified Design Flows

[Pressemitteilung]

MOUNTAIN VIEW, Calif., Aug. 25, 2020 — Synopsys, Inc. announced that Synopsys and TSMC have collaborated to deliver certified design flows for advanced packaging solutions using the Synopsys 3DIC Compiler product for both silicon interposer based Chip-on-Wafer-on-Substrate (CoWoS‑S) and high-density wafer-level RDL-based Integrated Fan-Out (InFO‑R) designs. 3DIC Compiler provides packaging design solutions required by today’s complex multi-die systems for applications like high-performance computing (HPC), automotive and mobile.

“Applications such as AI and 5G networking increasingly require higher levels of integration, lower power consumption, smaller form factors, and faster time to production, and this is driving the demand for advanced-packaging technologies,” said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. “TSMC’s Innovative 3DIC technologies such as CoWoS and InFO enable customer innovation with greater functionality and enhanced system performance at increasingly competitive costs. Our collaboration with Synopsys provides customers with a certified solution for designing with TSMC’s CoWoS and InFO packaging technologies to enable high productivity and faster time to functional silicon.”

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