C1E Stromsparmodus bei AMD

Necabo

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Hallo. Ich wüsste mal ganz gerne, welche AMD-Prozessoren den C1E Stromsparmodus unterstützen.

Fängt das schon mit der K8-Serie an?

Danke.
 

N1truX

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C1E ist ein Feature ab den K10 Prozessoren..
 

Dr@

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Zitat aus dem "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors":

10.2.4 C1 Enhanced (C1E) Halt State

C1E is a Stop Grant state like C3 supported by dual core mobile processors. The difference between C1E and C3 is that transition into C1E is not initiated by the operating system. The C1E state is initiated by an I/O transaction to the chipset when both cores transition into the C1 state. The chipset will either generate an SMI when receiving the I/O transaction.

Damit sind die Turion X2 ( K8 ) gemeint! Allerdings hat hier C1E nie wirklich funktioniert:

168 System May Hang When Exiting C1E or C3

Description
A link may fail to reconnect when exiting C1E or C3.
Potential Effect on System
The link may fail to reconnect when exiting C1E or C3 leading to a system hang.
Suggested Workaround
BIOS should set FidVidEn in the Power Management Control Low Register[PMM1[FidVidEn]] to 1b (Dev 3x80h[10] = 1b).
When implementing this workaround BIOS must clear AltVidEn in the Power Management Control Low Register[PMM1[AltVidEn]] to 0b (Dev 3x80h[11] = 0b).
Fix Planned
No
Quelle

Beim Nachfolger Griffin wars auch verbugged (Errata 316 & 365).

316 Incorrect CpuDid May Be Applied During ACPI States

Description
The processor may use an incorrect core clock divisor if it enters or exits the HTC-active state in a narrow window of time after it has applied the CpuDid for an ACPI power state transition. Under these conditions, the CpuDid from the current P-state as indicated by CurPstate (MSRC001_0063[2:0]) is used rather than the CpuDid from the ACPI power state.
Potential Effect on System
Unpredictable system behavior may result if an alternate voltage (altvid) is enabled for the ACPI power state, for example in C1E, and the CpuDid applied is less than that specified for the ACPI power state.
Suggested Workaround
Contact your AMD representative for information on a BIOS update.
Fix Planned
No

365 C1e Mode May Cause Unpredictable System Behavior

Description
Unpredictable system behavior may occur during C1e entry.
Potential Effect on System
Unpredictable system behavior.
Suggested Workaround
BIOS should use Centralized Link Management Controller (CLMC) features instead of C1e and should not set Interrupt Pending and CMP-Halt Register[C1eOnCmpHalt, SmiOnCmpHalt] (MSRC001_0055[28:27]).
Fix Planned
No

Und selbst bei den K10 funktioniert C1E nicht ohne Probleme!

400 APIC Timer Interrupt Does Not Occur in Processor C-States

Description
An APIC timer interrupt that becomes pending in low-power states C1e or C3 will not cause the processor to enter the C0 state even if the interrupt is enabled by Timer Local Vector Table Entry[Mask], APIC320[16]). APIC timer functionality is otherwise unaffected.
Potential Effect on System
System hang may occur provided that the operating system has not configured another interrupt source. APIC timer interrupts may be delayed or, when the APIC timer is configured in rollover mode (APIC320[17]), the APIC timer may roll over multiple times in the low-power state with only one interrupt presented after the processor resumes. The standard use of the APIC timer does not make this effect significant.
Suggested Workaround
Operating system software should enable another source of timer interrupts, such as the High Precision Event Timer, before it enters the C1 state by executing the HALT instruction and C1e is enabled through Interrupt Pending and CMP-Halt Register[C1eOnCmpHalt or SmiOnCmpHalt] (MSRC001_0055[28:27] are not 00b). For purposes of determining if C1e is enabled, the operating system should not sample MSRC001_0055 until after ACPI has been enabled.
Operating system software should enable another source of timer interrupts, such as the High Precision Event Timer, when the processor enters the C3 state.
It is possible for the system to implement a hardware fix to C1e mode on some processor revisions and some packages. This is indicated by OSVW[1] and no workaround is necessary when OSVW_Length >= 2 and OSVW[1] is zero. An operating system workaround for C3 mode is always necessary, regardless of the setting of OSVW[1].
Fix Planned
C1e state: Yes
C3 state: No

407 System May Hang Due to Stalled Probe Data Transfer

Description
Under highly detailed and specific internal timing conditions, a processor that has one or more processor cores in a cache-flushed state following a C1e exit, and one or more cores executing in C0 state, may not complete a data transfer for a probe.
Potential Effect on System
System hang.
Suggested Workaround
Contact your AMD representative for information on a BIOS update.
This workaround requires that Clock Power/Timing Control 2 Register[CacheFlushOnHaltTmr] (F3xDC[25:19]) is greater than 01h, which is true under normal circumstances.
Fix Planned
Yes
Errata 407 ist beschränkt auf die C2 Modelle Phenom II, Athlon II X2 (Athlon II X4 und Athlon X3 sind nicht betroffen) und Turion II.


Zusammenfassend kann man wohl sagen, dass seit dem Turion X2 C1E in AMD Prozessoren integriert ist. Leider funktioniert es nicht wirklich ohne Probleme. Mit dem C3 Stepping wird ein neuer Anlauf unternommen. Mal schauen obs dann richtig funktioniert.

Welchen Einfluss der MS Patch auf diese Fehler hat, kann ich nicht abschätzen. Das einige von geringeren Idle Leistungsaufnahmen berichten andere aber nicht, deutet für mich auf eine unterschiedliche Umsetzung der Mainbaordhersteller hin. Der beschriebene OS workaround zeigt aber auch den Einfluss des OS auf.


MfG @
 
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Ge0rgy

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Was mich verwirrt ist der text dass der Chipset per SMI-Interrupt den C1E auslösen würde ohne zutun des OS.
Nun gibt es aber z.b. im BIOS meines Mobos, nur 2 Optionen für C1E, "Disabled" und "Software SMI".
Wenn es aber eien HW-Sache des chipsets ist, wieso dann "Software SMI" ?

Irgendwie sit das alles durcheinander.
Irgendwo stand doch auch mal, dass die Regors C1E anders implementiert hätten als der Rest ihrer K10.5-Geschwister...?
 

Dr@

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Ja der Regor und das kommende C3 Stepping können "Hardware Initiated C1E":

2.4.3 C-states

C-states are processor power states in which the processor is powered but may or may not execute instructions. C0 is the operational state in which instructions are executed. All other C-states are low-power states in which instructions are not executed. The actions taken by the processor when a low-power state is entered are defined by [The ACPI Power State Control Registers] F3x[84:80]. C0 and C1 are ACPI-defined states, see the ACPI specification for details. C1E is an AMD specific state. When coming out of warm and cold reset, the processor is transitioned to the C0 state.

2.4.3.1 C1 Enhanced State (C1E)

The C1 enhanced state (C1E) is a stop-grant state supported by the processor. The C1E state is characterized by the following properties:
  • All cores are in the halt (C1) state.
  • The ACPI-defined P_LVL3 register has been accessed.
  • The chipset has issued a STPCLK assertion message with the appropriate SMAF for C1E entry. Note that [The ACPI Power State Control Registers] F3x[84:80] specify the processor clocking and voltage behavior in response to the C1E SMAF.
  • The processor has issued a STOP_GRANT message to the chipset.
General requirements for C1E:
  • The ACPI-defined C2 and C3 states must not be declared to the operating system.
  • C1E should only be enabled when the platform is in ACPI power management mode.

2.4.3.1.1 SMI Initiated C1E

When C1E is enabled and the processor detects that all cores have entered the halt state, the processor sends an IO write to the SMI command port in the chipset. This causes the chipset to generate an SMI. It is expected that the SMI targets all cores and therefore all cores enter SMM. The SMM handler may or may not place the system into the C1E state. See 2.4.3.1.2.1 [SMM Handler Requirements for C1E] for a description. SMI initiated C1E is only supported on single link systems.

2.4.3.1.3 Hardware Initiated C1E

When C1E is enabled and the processor detects that all cores have entered the halt state, the processor sends an IO read to the ACPI-defined P_LVL3 register. This places the system into the C1E state. Hardware initiated C1E is only supported on single link systems. Hardware initiated C1E is recommended over SMI initiated C1E for revisions where both are supported. See Table 2.
Quelle


MfG @
 
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Necabo

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Das sind ja schon mal massig Infos! Herzlichen Dank. :)

Bei nem AM2 Opteron mit F3 Stepping kann man das wohl knicken.
 

p4z1f1st

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*hier stand mist*
 
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