HBM3 IP Solution Delivers Maximum Memory Bandwidth of 921 GB/s for High-Performance Computing, AI, and Graphics SoCs
MOUNTAIN VIEW, Calif., Oct. 7, 2021 /
PRNewswire/ —
Highlights of this Announcement:
- The DesignWare HBM3 Controller, PHY, and Verification IP reduces integration risk and maximizes memory performance in 2.5D multi-die systems
- Low-latency HBM3 Controller with flexible configuration options enhance memory bandwidth
- Pre-hardened or configurable HBM3 PHY in 5-nm process operates at 7200 Mbps for up to 2X the data rate and improves power efficiency by up to 60% compared to HBM2E
- Verification IP and memory models for ZeBu and HAPS offer an end-to-end solution for rapid verification closure from IP to SoC
- Synopsys’ 3DIC Compiler, an integrated multi-die design and analysis platform, provides a comprehensive HBM3 auto-routing solution for rapid and robust design development
Synopsys, Inc. (Nasdaq:
SNPS) today announced the industry’s first complete HBM3 IP solution, including controller, PHY, and verification IP for 2.5D multi-die package systems. HBM3 technology helps designers meet essential high-bandwidth and low-power memory requirements for system-on-chip (SoC) designs targeting high-performance computing, AI and graphics applications. Synopsys’
DesignWare® HBM3 Controller and PHY IP, built on silicon-proven HBM2E IP, leverage Synopsys’ interposer expertise to provide a low-risk solution that enables high memory bandwidth at up to 921 GB/s.
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